Fetch Decode Execute Cycle

[Overdriven]

Hey all -_- Currently doing some work on Computer Systems and this is the last thing I'm having issues with (Just this and I've got it completely done)

Anyone who could explain this to me? What does it do after grabbing from the registers? =<

Need teh help!


Cheers,


Over.


EDIT:

Yep, I googled it - Nope; still need help.

 

[anattic]

They're pipeline stages in a microprocessor. Typically, this means you start preparing the next command as you execute the one behind it. "Fetch" gets the command from program memory (or the instruction cache), "Decode" determines what processor resources the command will require (and loads in the arguments), "Execute" performs the command. In RISC-land, you then have "Address" which is sort-of "Execute-part-2" and "Writeback" which pushes the result out to the destination register (or memory).

Overview on pipelining: http://en.wikipedia.org/wiki/Pipeline_(computer)
Classical RISC pipeline: http://en.wikipedia.org/wiki/Classic_RISC_pipeline

Thing about a pipelined micro is that the commands in the pipe behind a jump/branch instruction may be redundant and need flushing out. Modern micros try to mitigate this with branch prediction etc. Blurb: http://en.wikipedia.org/wiki/Branch_delay_slot

 

[Overdriven]

Jah.. Okay, want to become my tutor for the next 2 years?

Cheers for the reply, cleaned it up a little for me.